Specifications for the Time-to-Digital Converter Histogramming Unit
- Sampling interval:
- 2ns, 4ns, 8ns, or 16ns nominal, software selectable
- Timing accuracy:
- 50ppm at 25°C, or one sampling interval, whichever is greatest
- Minimum pulse spacing:
- 2ns or one sampling interval, whichever is greatest
- Data loss rate:
- zero (subject to overflow criteria below)
- Overflow criteria:
- Burst rate:-
16 detections in each of up to 64 consecutive frames, each frame being 16 sampling periods long (e.g. up to 1024 hits in 2µs). - Mean rate:-
1 detection per 100ns sampling intervals indefinitely (worst case)
- Burst rate:-
- Dead time between cycles:
- 144 sampling periods
- Time window limits (in steps of 256 sample intervals):
-
- Suppress time:-
Up to cycle time minus 256 sample intervals. - Cycle time:-
Up to 32k sample intervals.
- Suppress time:-
- Trigger Pulse:
- Internally generated from external trigger source.
- Cycles per experiment:
- Unlimited, with up to 224 per computer start instruction
- Histogram length:
- 32k bins
- Histogram height:
- 16 bit (wrap on overflow) on board; standard software collects to 32 bits
- Power supply:
- 110-240v AC 50-60Hz
- Trigger and signal inputs:
- User hardware selectable: ECL terminated 50 ohms to -2V, or TTL terminated 50 ohms to groung. NIM/TTL option. (±5v outputs available for pre-amp) +ve or -ve edges.
- Trigger output:
- TTL positive edge
- Optional PC interface:
- ISA bus card/PCMCIA adaptor, or alternative USB option.
- Optional IBM PC software:
-
Multiple experiment with summation to 32 bits to give GRAMS/AI compatible data file (Software can be supplied to allow the TDC to operate directly from GRAMS/AI
"C" libraries for full TDC control.
Source provided to supplement documentation.
- TDC housing:
- 11 x 11.5 x 2.5 inch bench unit with connections at rear LED indicators for Power, Overflow, Reset and Measurement in progress (MIP)
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Last updated: Thursday, September 15, 2005, 11:55
© Kore Technology Limited 2005